1. Technical Field
The embodiments herein relate to DRAMs, such as a DRAM with a decoupling capacitance calibration circuit.
2. Description of the Prior Art
DRAM operations use varying amounts of supply current according to the processes the DRAM is performing. In order to ensure the DRAM does not experience large voltage drops during normal operations, a decoupling capacitance (decap) corresponding to the highest expected voltage drop is often included in the design. This allows charge to be stored in reserve, which can be used for higher current operations, to reduce demand on the power supply.
With the development of semiconductor technology, however, DRAMs are increasingly being used for lower power operations. In a low power DRAM design, local voltage power domains might be powered down during power down mode. When exiting power down mode, a higher decoupling capacitance may cause the DRAM to take a longer time to power up the local voltage power domains.